The present invention relates to packaging of integrated circuits and to soldering methods.
Integrated circuit dies (“chips”) can be attached to a lead frame and then packaged in a ceramic or plastic carrier. The leads of the lead frame can then be soldered to a printed circuit board (PCB). Alternatively, the chip can be soldered directly to the PCB (“flip chip” packaging). The flip chip packaging reduces the package size and shortens the electrical connections between the die and the PCB, but the flip chip packaging is vulnerable to solder failures caused by thermal expansion and contraction. The solder failures are due to the differences in the coefficient of thermal expansion (CTE) between the die and the PCB.
The CTE mismatch has been addressed by providing an intermediate substrate between the die and the PCB, with an intermediate CTE. For example, in a ball grid array (BGA) package, the die is flip-chip attached to the intermediate substrate (“BGA substrate”), and the BGA substrate is soldered to the PCB. The BGA substrate provides interconnect lines between the die and the PCB. A silicon die may have a CTE of about 2.7 ppm/° C. (parts per million per degree Centigrade); a PCB made of FR4 can have a CTE of about 20 ppm/° C.; a BGA substrate made from BT (bis-maleimide triazine) has a CTE of about 16 ppm/° C., and a BGA substrate made from ceramic has a CTE of about 9 ppm/° C.
In addition to reducing the thermal stresses, the intermediate substrate may allow a smaller die size by allowing the die to have smaller contact pads with a reduced pitch. The minimum size and pitch of the die's contact pads is limited by the size and pitch of the contact pads on the substrate to which the die is attached. For example, if the die is flip-chip bonded to a BT substrate, the size and pitch of the die's contact pads can be smaller than if the die is attached to an FR4 substrate (PCB).
The intermediate substrate may also reduce the PCB area taken by the die because the intermediate substrate may redistribute the die's contact pads. The position of the die's contact pads is restricted by the die's circuitry. The BGA substrate's contact pads that are bonded to the PCB are not restricted by the die's circuitry. For example, the die may have contact pads only on the periphery, but the BGA substrate's contact pads attached to the PCB may be evenly distributed over the BGA area.
Further, if multiple dies are mounted on a single intermediate substrate, the dies can be interconnected by interconnects in the intermediate substrate without using the PCB routing resources. This leads not only to saving the PCB area but also to shorter interconnections between the dies and hence to a better electrical performance (higher speed and lower power consumption, inductance and capacitance).
FIG. 1 illustrates another package with two intermediate substrates 110, 120 between dies (ICs) 124 and PCB 130. Intermediate substrate 110 is a BT substrate, soldered to the underlying PCB 130 with solder balls 134. Intermediate substrate 120 is a silicon interposer attached to the top surface of BT substrate 110 by an adhesive (not shown). Silicon interposer 120 includes metal layers 136 formed over silicon substrate 140 and separated by dielectric layers 144. Dies 124 are attached to interposer 120 with their contact pads facing up. The dies' contact pads are wire bonded to contact pads 136C.1 provided by metal layers 136. The wire bonding is done with bond wires 150. Contact pads 136C.2 on top of the interposer are wire bonded to contact pads 360 on top of BT substrate 110 using bond wires 160. Interconnect lines made from layers 136 connect the contact pads 136C.1 to the contact pads 136C.2.
Metal layers 136 provide interconnects between the dies 124. The interconnects can be manufactured on silicon interposer 120 with a higher density and higher electrical performance than on BT substrate 110. There is no CTE mismatch between silicon substrate 120 and silicon dies 124.
For commercial reasons, a manufacturer may sell packaging substrates consisting substantially of a silicon interposer 120 and a BT substrate 110 (FIG. 2). Then the buyers of the packaging substrates attach the dies 124 and the PCBs 130 to the packaging substrates.
Alternative packaging substrates and packaging techniques are desirable.
Soldering: When multiple soldering operations are performed to form different solder joints, each subsequent soldering operation should not destroy the solder joints formed in the previous operations. This can be achieved, by a solder hierarchy, i.e. a hierarchy of the solder melting temperatures. Each subsequent soldering operation is performed with a solder having a lower melting temperature then the solders used in the previous operations, so the solders used in the previous operations do not melt. It is desirable to develop techniques that relax the solder hierarchy requirements.